1. Field of the Invention
The invention generally relates to emitter follower logic circuits using complementary transistors and, more particularly, to such circuits characterized by unity gain, no level shift, low power consumption and high speed in responding to input signal transitions of either increasing or decreasing sense.
2. Description of Prior Art
As is well known, a capacitively loaded emitter follower circuit using complementary transistors such as shown, for example, in FIG. 8-36 on page 304 of the text Pulse, Digital and Switching Waveforms, by J. Millman and H. Taub, McGraw Hill, 1965, provides an output waveform having rising edges and falling edges that follow (with comparable speed) the corresponding rising and falling edges of the input waveform. In the example given, however, the bases of the series-connected complementary transistors are driven by the same input waveform whose voltage excursions turn each transistor on and off.
This necessitates a relatively large input voltage excursion, at least equal to the sum of the V.sub.be 's for forward biasing the emitter-base junctions of the two transistors, and represents a significant power expenditure.
Furthermore, the cited emitter follower circuit provides less than unity gain so that the signal losses must be overcome by auxiliary drivers in order to cascade the circuits. Additionally, the cited circuit shifts the level of the signal between input and output, by at least one V.sub.be, requiring a translator to eliminate the level shift when designing cascaded logic.
It is desirable that the complementary emitter follower circuit be modified to avoid level shift, and to provide unity gain while reducing the required input voltage excursion so as to maximize the response speed of the circuit.